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23 thg 5, 2019 · • Quantitatively motivated ISA optimization and code generation • Implications for more complex microarchitectures (e.g., superscalar) • Tagged memory: tag cache vs. native support in DRAM • Complete tool-chain: linker, debugger • C++ compilation to CHERI(+COOP) • OS support, larger application corpus • CHERI and ISO C/POSIX APIs ...
Hardware that directly understands object model (CHERI) We think CHERI is a unique point in the space: directly conveys some high-level notions in hardware scales better than current protection mechanisms retains broad compatibility with languages (C)
We extend our CHERI ISA and processor prototype with sealed capabilities and hardware-accelerated object invocation, and extend the CHERI software stack (LLVM compiler [30] and FreeBSD OS [33]) with a domain-transition calling convention and a …
The CHERI architecture's support for fine-grain memory protection and scalable compartmentalization promises to revolutionise our ability to protect personal data and provide strong defences against malware on mobile devices and in the cloud
CHERI will provide a supportive framework for a broad variety of security-sensitive activities; while not itself a distributed system, CHERI could form a sound foundation for various forms of distributed trustworthiness.
We explain the principles underlying these language variants, and their grounding in CHERI’s multiple architectural instantiations: CHERI-MIPS, CHERI-RISC-V, and Arm’s Morello.
Shared code base with Arm’s CHERI Morello CheriBSD fully supports CHERI-RISC-V (version 9).
The CHERI Task Group (TG) is working on the RISC-V hardware ISA changes, with the draft specification document now available from the CHERI TG’s repository [1].
26 thg 2, 2025 · CHERIoT is a variant of CHERI based on the 0.9.5 RISC-V proposed standard; it is for RV32E implementations for IoT devices. Silicon for OpenTitan is expected this year.
This report is a high-level introduction to CHERI. The report describes our architectural approach, CHERI’s key microarchitectural implications, our approach to formal modeling and proof, the CHERI software model, our software-stack prototypes, further reading, and potential areas of …
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